2024

IGZO thin-film transistor reliability: the last standing roadblock for memory applications, A. Chasin¹, P. Rinaudo^1,2, Y. Zhao^1,2, H. Dekkers¹, M. van Setten¹, S. Subhechha¹, A. Kruv¹, D. Matsubayashi¹, A. Pavel¹, Y. Wan¹, K. Trivedi¹, N. Rassoul¹, A. Belmonte¹, G. S. Kar¹, B. Kaczer¹, and J. Franco¹, ¹imec, Belgium, ²U. Leuven, Belgium

Monolithic 3D Integration of Functionally Diverse 2D Devices, S. Das, Pennsylvania State U.

Variability in Hafnia-based Ferroelectrics: A Phase-Field Simulation based Perspective, R. Koduru and S. K. Gupta, Purdue U.

Hafnia-Based FeRAM for High-Density, High-Speed Embedded Memory, C. Neumann, S.-C. Chang, B. Granados Alpizar, S. Shivaraman, B. Bangalore Rajeeva, C.-C. Lin, J. Peck, N. Kabir, Y.-C. Liao, W. Chakraborty, N. Haratipour, I.-C. Tung, V. Nikitin, H. Li, G. Allen, T. Hoff, A. Oni, S. Atanasov, T. Tronic, A. Roy, M. Metz, I. Young, J. Kavalieros, and U. Avci, Intel

CFET Technology for Future Logic Scaling, S. Liao, TSMC

Gate Stack Innovations for Gate-All-Around (GAA) Device Architecture to Continue Transistor Scaling, R. Bao, D. Guo, and H. Bu, IBM

Pioneering Innovation for Next Generation 3D Memory Era, K. Park, J. Kim, Y. S. Tak, I. Zoh, S. H. Jang, S. W. Jung, S. Y. Yang, G. H. Yon, H. J. Kim, Z. Wu, S. C. Oh, I. Jeon, D. S. Lee, J. Kim, J. M. Oh, J. K. Lee, I.-M. Park, S. U. Han, K. Kim, M. H. Cho, H. J. Lim, H. M. Choi, W. Kim, J. Han, D. Ha, S. Park, J. Han, H. S. Kim, Y. J. Song, B. J. Gu, S. J. Ahn, S. J. Hyun, and J. Song, Samsung

Device Engineering for High-Performance Gallium Oxide Electronics, A. Deenan, N. Wriedt, C. Joishi, J. Hwang, S. A. Ringel, H. Zhao, J. McGlone, and S. Rajan, Ohio State U.

2023

Enabling Gate Pitch Scaling in the Angstrom Era, A. Penumatcha, Intel

Radiation Effects and Reliability in 3D Integrated Circuits, E. X. Zhang¹, S. Toguchi², R. D. Schrimpf³, M. L. Alles³, and D. M. Fleetwood³, ¹U. of Central Florida, ²Microchip Technology Inc., ³Vanderbilt U.

Interconnects: New Materials for High Conductivity, D. Gall, Rensselaer Polytechnic Institute

Protonic Electrochemical Synapses for Analog Deep Learning and Beyond, B. Yildiz, MIT

Entering a New Era of Nanosheet FET-based Device Architectures with Increased FEOL-BEOL Synergies, A. Veloso, G. Eneman, P. Matagne, B. Vermeersch, H. Arimura, B. O'Sullivan, C. Porret, and N. Horiguchi, imec, Belgium

Oxide Semiconductor Transistors for LSI Application, M. Kobayashi, U. Tokyo, Japan

Ovonic Threshold Switching (OTS) Device for Selector Applications, J. Lee, S. Ban, and H. Hwang, POSTECH, Korea

Interface Trapping and Scattering in 4H-SiC MOSFETs, S. Dhar, Auburn U.

2022

Device Engineering and Benefit Maximization for Advanced Cryo, H.-L. Chiang, J.-J. Wu, P.-J. Liao, T.-C. Chen, C.-S. Chang, X. Bao, J. Cai, M. F. Chang, H. Chuang, C. H. Diaz, H.-S. P. Wong, M. Passlack, and I. Radu, TSMC, Taiwan

Efficient Control of 2D Magnets, C. Gong, U. Maryland

EWF control of advanced high-thermal-budget RMG gate stack, H. Arimura, J. Franco, S. Brus, E. Dentoni Litta, and N. Horiguchi, imec, Belgium

Ferroelectric field-effect transistors: Reliability and logic compability, D. Das, N. Tasneem, and A. Khan, Georgia Institute of Technology

Hardware Algorithm Co-optimization for Scalable Analog Compute Technology, T. Ando, IBM

Interfaces between GaN and AlN: epitaxy, properties and devices, H. G. Xing, Cornell U.

Oxide Semiconductor Back-end-of-line(BEOL)-CompatibleTransistors and Memories, X. Gong, K. Han, S. Samanta, C. Sun, C. Wang, and Z. Zheng, National U. of Singapore, Singapore

Reduced Contact Resistances for Moire Lattice Interfaces of MoS₂ and otherLayeredCompounds, J. Robertson¹, Z. Zhang¹, and Y. Guo², ¹U. Cambridge, UK, ²Wuhan U., China

2021

A New Era of Integrated Molecular Electronics: A Programmable Single-Molecule Biosensor on a Semiconductor Chip, B. Merriman, Roswell Biotechnologies

Atomic-layer-deposited atomically thin In₂O₃ channel for BEOL logic and memory applications, P. D. Ye, Purdue U.

CMOS Logic Technology Scaling Beyond FinFETs - In memoryof the legacy of T. P. Ma, H. Bu, D. Guo, D. Dechene, V. Narayanan, A. Chen, J. Rozen, and M. Frank, IBM

Dielectrics for Devices from CMOS Extension to Beyond-CMOS A personal research journey owing to the inspiration, guidance, and support of Prof. Ma, A. Chen, SRC

Ferroelectric Materials and Devices for Disruptive Semiconductor Technology, J. Heo¹, D.-H. Choe¹, H. Lee¹, S. Jo¹, H. Bae¹, S. G. Nam¹, J.-H. Kim¹, E. Lee¹, Y. Kim², H. Kim², Y. Lee¹, T. Moon¹, and H. Lee¹, ¹Samsung Advanced Institute of Technology, Korea, ²Sungkyunkwan U., Korea

Functional Integration on III-V Nanowires, L.-E. Wernersson, Lund U., Sweden

Hafnia-based Ferroelectrics, S. Slesazeck¹, S. Lancaster¹, M. Engl¹, and T. Mikolajick^1,2, ¹NaMLab gGmbH, Germany, ²TU Dresden, Germany

High-Frequency Ga₂O₃ FETs and Interface Related Challenges in Their Development, M. Higashiwaki, T. Kamimura, and S. Kumar, National Institute of Information and Communications Technology, Japan

Mark Reed and the Birth of Nanoelectronics, A. Seabaugh¹, W. R. Frensley², and J. N. Randall³, ¹U. Notre Dame, ²UT Dallas, ³Zyvex Labs

Mark Reedand the Birthof Molecular Electronics, J. M. Tour, Rice U.

RF-Biased Atomic Layer Annealing of Polycrystalline Materials at Low Temperature on Insulators, A. J. McLeod¹, S. T. Ueda¹, J. Spiegelman², and A. C. Kummel¹, ¹UCSD, ²RASIRC

2020

Interface Effects on the Reliability of Hafnium Oxide-Based Ferroelectric Memories, P. C. McIntyre, Stanford U.

Van der Waals Integration beyond 2D Materials, X. Duan, UCLA

Progress and issue in oxide semiconductors, H. Hosono^1,2, ¹Tokyo Institute of Technology, Japan, ²National Institute for Materials Science, Japan

Insulators for 2D Nanoelectronics: Expectations vs. Reality, Y. Y. Illarionov^1,2, T. Knobloch¹, and T. Grasser¹, ¹TU Wien, Austria, ²Ioffe Institute, Russia

Discovery and transistor applications of polarization-induced 2D hole gases at polar semiconductor heterojunctions, D. Jena, R. Chaudhuri, S. Bader, K. Nomoto, and H. Xing, Cornell U.

Reliability Physics of Post-Moore Era Electronic Devices, M. A. Alam, Purdue U.

Discoveryand Understanding of Single-Atom Memory Effect in 2D Atomic Sheets, D. Akinwande, UT Austin

65K-RRAM-Array Analog Conductance Relaxation Characterization For Neural Network Inference, W. Wan and H.-S. P. Wong, Stanford U.

Dielectric-Diamond Interfaces, Y. Yang, Y. Yao, X. Wang, F. A. Koeck, and R. J. Nemanich, Arizona State U.

MOCVD based dielectrics on GaN: Impact of growth conditions, composition and polarity, I. Sayed and U. Mishra, UCSB

2019

Dielectric Interface and Materials Challenges for Quantum Computing, R. Pillarisetty, Intel

Narrow interconnects: The search for new metals, D. Gall, A. Jog, E. Milosevic, Rensselaer Polytechnic Institute

The Next Era of Scaling in Electronics, S. Datta, U. Notre Dame

Hafnium-based Vertical Ferroelectric FET: A New Mass Storage Device, J. Van Houdt, ¹imec, Belgium, ²U. Leuven, Belgium

Hardware Implementation of RRAM based Binarized Neural Networks, Z. Zhou¹, P. Huang¹, Y.Z. Zhang¹, Y. C. Xiang¹, W. S. Shen¹, Y. D. Zhao¹, Y. L. Feng¹, B. Gao², H. Q. Wu², H. Qian², L. F. Liu¹, X. Zhang¹, X. Y. Liu¹, and J. F. Kang¹, ¹Peking U., China, ²Tsinghua U., China

Recent progress towards ternary logic devices for extreme low power architecture, B. H. Lee¹, S. Kim¹, K. Kim¹, H. Lee¹, S. Kang², M. M. Sung³, ¹GIST, Korea, ²Pohang Institute of Science and Technology, Korea, ³Hanyang U., Korea

Future Directions in > 100 GHz Devices, M. J. W. Rodwell, B. Markman, Y. Fang, UCSB

Engineering High Performance Oxide Memristors, J. L. MacManus-Driscoll, U. Cambridge, UK

Intermixing-protected interfacial phase-change memory to make better superlattices for future PCM, J. Tominaga, AIST, Japan

Growth of Topological Insulators and Related Heterostructures, C. L. Hinkle, U. Notre Dame

2018

Interfaces for CMOS bioelectronics, K. Shepard, Columbia U.

Future Scaling of Advanced Logic Devices, H. Bu, IBM

ALD for Semiconductor Interfaces, G. Wilk, ASM America

Surface Processes for Selective Atomic Layer Deposition, S. F. Bent, Stanford U.

Quasi-Static Negative Capacitance (QSNC): Science Fact or Science Fiction?, T. P. Ma, Yale U.

Investigating Interface States and Border Traps in the Oxide/MoS₂ System, P. K. Hurley¹, P. Zhao², P. Bolshakov², G. Mirabelli¹, E. Caruso¹, F. Gity¹, S. Monaghan¹, J. Lin¹, L. Walsh¹, K. Cherkaoui¹, C. M. Smyth², A. Khosravi², A. Azcatl², C. L. Hinkle², R. M. Wallace², and C. D. Young², ¹Tyndall National Institute, Ireland, ²UT Dallas

Dopant-Free Carrier Selective Contacts for Highly Efficient Si Solar Cells, A. Javey, UC Berkeley

Physics in Charge Injection Induced On-Off Switching Mechanism of Resistive Random Access Memory (ReRAM) and Superlattice GeTe/Sb₂Te₃ Phase Change Memory (iPCM), K. Shiraishi, Nagoya U., Japan

2017

Data Mining for New Two- and One-dimensional Weakly Bonded Solids and Application to Two-dimensional Phase Change Materials, G. Cheon, D. A. Rehn, Y. Zhou, and E. J. Reed, Stanford U.

Electronic Label-Free Biosensing Assays, M. A. Reed, Yale U.

Ferroelectric fluorite structured oxides: Materials fundamentals, switching, wake- up, and applications in electronics and energy, M. H. Park and C. S. Hwang, Seoul National U., Korea

Enabling Continued Device Scaling: An Equipment Supplier's Perspective, D. Hemker, Lam Research

Emerging memories: High density integration challenges, N. Ramaswamy, Micron Technology

Oxide Electronics Harnessing Electronic Phase Transitions, S. Datta¹, N. Shukla¹, M. Jerry¹, A. Parihar², and A. Raychowdhury², ¹U. Notre Dame, ²Georgia Institute of Technology

Interfaces and contacts in next generation silicon photovoltaics, P. Stradins, W. Nemeth, and S. Harvey, NREL

Band-to-band tunneling devices from two-dimensional materials, A. Prakash, P. Wu, and J. Appenzeller, Purdue U.

2016

Addressing Process Integration Challenges for 2D Semiconductor Materials, R. M. Wallace, UT Dallas

Interface Engineering for High Performance Insulator-Protected MIS Photosynthesis Cells, P. C. McIntyre, Stanford U.

Material Innovation Ferroelectric Hafnium Oxide: Towards Cheaper Memories, Steeper Slopes and New Value Adders for HKMG, J. Müller¹, H. Mulaosmanovic², S. Müller^2,3, P. Polakowski¹, J. Ocker^2,3, M. Noack^2,3, S. Riedel¹, T. Ali¹, M. Peši?², U. Schröder², S. Slesazeck², T. Mikolajick^2,4, ¹Fraunhofer, Germany, ²NaMLab, Germany, ³Ferroelectric Memory GmbH, Germany, ⁴TU Dresden, Germany

Perspective on III-V Tunnel-FETs: bridging the gap between ideal device design and experimental realizations through calibration, A. S. Verhulst¹, Q. Smets¹, J. Bizindavyi^1,2, D. Verreck^1,2, S. El Kazzi¹, A. Alian¹, J. Franco¹, Y. Mols¹, A. Vandooren¹, R. Rooyackers¹, D. Lin¹, A. Mocuta¹, B. Sorée^1,2,3, G. Groeseneken^1,2, N. Collaert¹, and M. M. Heyns^1,2, ¹imec, Belgium, ²U. Leuven, Belgium, ³U. Antwerp, Belgium

Critical issues and Challenges of High k Gate Stacks for Ge/GOI MOSFETs, S. Takagi, M. Ke, Y. Xiao, R. Zhang, and M. Takenaka, U. Tokyo, Japan

Negative Capacitance and Its Implications for Low Voltage Transistors, S. Salahuddin, UC Berkeley

2D/3D Tunnel FETs: Toward Green Transistors and Sensors, K. Banerjee, UCSB

III-V Nanowire MosFETs and Tunnel FETs, L.-E. Wernersson, Lund U., Sweden

2015

Monolayer Organic Films for Nucleation of ALD on Single Layer Graphene and TMD surfaces, J. H. Park¹, I. Kwak¹, E. Chagarov¹, K. Sardashti¹, H. C. P. Movva², H. Chou², S. K. Banerjee², S. Fathipour³, S. K. Fullerton-Shirey³, A. Seabaugh³, S. Vishwanath⁴, H. G. Xing⁴, P. Choudhury⁵, and A. C. Kummel¹, ¹UCSD, ²UT Austin, ³U. Notre Dame, ⁴Cornell U., ⁵New Mexico Tech

Physics of electronic transport in low-dimensionality materials for future FETs, M. V. Fischetti, W. G. Vandenberghe, A. S. Negreira, Z.-Y. Ong, and B. Fu, UT Dallas

Silicon at the two-dimensional limit: the debut of the silicene transistor, A. Molle, CNR-IMM, Italy

GaN-based HEMTs for High-voltage and Low-loss Power Applications, M. Kuzuhara, J. T. Asubar, and H. Tokuda, U. Fukui, Japan

Materials and Process Controls in Germanium Gate Stacks, A. Toriumi, U. Tokyo, Japan

Two-dimensional Layered Materials and Nano-scale Devices, W. Zhu, UIUC

Ultra low-k insulating materials for advanced nanoelectronics, M. R. Baklanov, imec, Belgium

Microscopic Aspects of Conductive Filaments Evolution in Metal Oxide RRAM devices, B. Magyari-Köpe and Y. Nishi, Stanford U.

2014

From global and local Ge integration approaches on Si(001): Novel insights by advanced synchrotron XRD techniques, T. Schroeder^1,2, M. Zoellner¹, G. Capellini¹, O. Skibitzki¹, F. Montalenti³, A. Marzegalli³, M. I. Richard⁴, T. Schuelli⁴, Y. Yamamoto¹, P. Storck⁵, and B. Tillack^1,6, ¹IHP, Germany, ²TU Brandenburg, Germany, ³U. di Milano, Italy, ⁴European Synchrotron Radiation Facility, France, ⁵Siltronic, Germany, ⁶TU Munich, Germany

High k oxides on (In)GaAs surfaces studied by synchrotron radiation photoemission, T. W. Pi¹, Y. T. Fanchiang², Y. H. Lin², T. H. Chiang³, K. Y. Lin², Y. K. Su³, C. H. Wei¹, Y. C. Lin¹, G. K. Wertheim⁴, J. Kwo³, and M. Hong², ¹National Synchrotron Radiation Research Center, Taiwan, ²National Taiwan U., Taiwan, ³National Tsing Hua U., Taiwan, ⁴Woodland Consulting

Single-crystal oxide insulators grown epitaxially on GaAs, Ge and GaN by ALD, R. G. Gordon, X. Liu, X. Wang, and S. B. Kim, Harvard U.

Dielectric/III-N Interfaces with Nitridation Interlayer for GaN Power Electronics, K. J. Chen, S. Yang, Z. Tang, and S. Huang, Hong Kong U. Science and Technology, Hong Kong

2D Materials Growth and Prospects, L. Colombo¹, S. Banerjee², R. M. Wallace³, and C. L. Hinkle³, ¹Texas Instruments, ²UT Austin, ³UT Dallas

Carrier response in electric-field-induced bandgap of bilayer graphene, K. Nagashio, U. Tokyo, Japan

Contact engineering, chemical doping and heterostructures of layered chalcogenides, A. Javey, UC Berkeley

In-situ probing surfaces of oxide electronic materials with atomic resolution: physical functionalities and memristive mechanisms, S. V. Kalinin, Oak Ridge National Laboratory

Memory technologies for the terabit era: a paradigm shift, J. Van Houdt, imec, Belgium

Memcomputing: computing with and in memory, M. Di Ventra¹, F. L. Traversa¹, Y. V. Pershin², ¹UC San Diego, ²U. South Carolina

Reliability challenges of high mobility channel technologies: SiGe, Ge and InGaAs, J. Franco¹, B. Kaczer¹, Ph.J. Roussel¹, M. Cho¹, T. Grasser², H. Arimura¹, D. Cott¹, J. Mitard¹, L. Witters¹, N. Waldron¹, D. Zhou¹, A. Alian¹, A. Vais¹, D. Lin¹, K. Martens¹, M. A. Pourghaderi¹, S. Sioncke¹, N. Collaert¹, A. Thean¹, M. Heyns, and G. Groeseneken³, ¹imec, Belgium, ²TU Wien, Austria, ³U. Leuven, Belgium

Evaluation of thermal properties of nanoscale MOSFETs and thermal aware device design of nano devices, K. Uchida^1,2, A. Shindome¹, T. Takahashi^1,2, T. Matsuki³, T. Shinada³, and Y. Inoue³, ¹Keio U., Japan, ²CREST, Japan, ³AIST, Japan

2013

Schottky Barrier Height Engineering for Low Resistance Contacts to Ge and III-V Devices, K. Saraswat, J.-Y. Lin, A. Nainani, A. Roy, G. Shine, and Z. Yuan, Stanford U.

Growth and characterization of Silicene, Germanene and other 2D layered materials, A. Dimoulas, D. Tsoutsou, E. Xenogiannopoulou, E. Golias, P. Tsipas, and S. Kassavetis, NCSR DEMOKRITOS, Greece

SymFET: A novel Graphene-Insulator-Graphene Tunneling Device, D. Jena, U. Notre Dame

Modeling SET and RESET transients in Hf-based RRAM devices using the Hourglass approach, R. Degraeve¹, A. Fantini², N. Raghavan^1,2, Y. Y. Chen^1,2, L. Goux¹, S. Clima¹, S. Cosemans¹, B. Govoreanu¹, D. J. Wouters^1,2, Ph. Roussel¹, G. S. Kar¹, G. Groeseneken^1,2, and M. Jurczak¹, ¹imec, Belgium, ²U. Leuven, Belgium

Overcoming critical instabilities at the interfaces of scaled HfO₂/Al₂O₃/Si gate stacks on In_0.53Ga_0.47As-On-Insulator, C. Marchiori¹, M. El Kazzi¹, L. Czornomaz¹, D. Pierucci², M. Silly², F. Sirotti², E. Uccelli¹, M. Sousa¹, and J. Fompeyrine¹, ¹IBM, Switzerland, ²Synchrotron SOLEIL, France

Heavily doped epitaxially grown source in InGaAs MOSFET for high drain current density, Y. Miyamoto¹, T. Kanazawa¹, Y. Yonai¹, A. Kato¹, K. Ohsawa¹, M. Oda², T. Irisawa², and T. Tezuka², ¹Tokyo U. Technology, Japan, ²AIST, Japan

Reducing EOT and Interface Trap Densities of High-k/III-V Gate Stacks, S. Stemmer¹, V. Chobpattana¹, R. Engel-Herbert², B. Mazumder¹, T. E. Mates¹, and W. J. Mitchell¹, ¹UCSB, ²Penn State U.

Materials Selection and Device Design for Low Power Tunnel Transistors, S. Datta, Penn State U.

Disorder Induced Gap States at the High-k/III-V Interface, E. M. Vogel, Georgia Institute of Technology

2012

Physics and Chemistry of the High k/InGaAs Interface for High Mobility Channel MOSFET, J. Kwo¹, M. Hong², T.-W. Pi³, W. W. Pai², Y. M. Chang², M. L. Huang¹, Y. C. Liu¹, C. A. Lin¹, T. D. Lin², Y. H. Chang¹, and W. C. Lee¹, ¹National Tsing Hua U., Taiwan, ²National Taiwan U., Taiwan, ³National Synchrotron Radiation Research Center, Taiwan

XPS Studies of Oxides on III-V, R. M. Wallace, UT Dallas

Weakly Interacting Epitaxial Systems: the Semiconductor/SrTiO₃ Case, G. Saint-Girons¹, A. Danescu¹, B. Gobaut¹, J. Penuelas¹, G. Grenet¹, G. Renaud², N. Blanc², V. Favre-Nicollin², M. El Kazzi³, F. Sirotti³, and M. Silly³, ¹Ecole Centrale de Lyon, France, ²CEA, France, ³Synchrotron SOLEIL, France

Graphene Bilayer Pseudospin FETs and 2D-2D Tunnel FETs, C. Corbet, D.Reddy, S. Kang, D. Basu, S. Kim, L. F. Register, E. Tutuc, and S. K. Banerjee, UT Austin

Strained InGaSb Metamorphic Growth and High-k Oxides Interfaces for P-Channel MOSFETs, S. Oktyabrsky, A. Greene, S. Madisetti, M. Yakimov, R. Moore, and V. Tokranov, SUNY Albany

Mechanism of RRAM Operations in HfO₂-based Devices, G. Bersuker, SEMATECH

Fundamental Aspects of HfO₂-based High-k Metal Gate Stack Reliability and t_inv-Scaling for MGHK CMOS Technologies, E. Cartier, IBM

Internal Photoemission at Ge/Oxide and A_III-B_V/Oxide Interfaces, V. V. Afanas’ev, H.-Y. Chou, M. Houssa, and A. Stesmans, U. Leuven, Belgium

2011

Ultrathin EOT scaling of high-k/metal gate stacks, L.-Å. Ragnarsson, M. Cho, T. Chiarella, J. Mitard, T. Schram, E. Röhr, L. Witters, M. Togo, N. Horiguchi, and A. Thean, imec, Belgium

Energy Efficient Computing Technologies Towards the End of Silicon Scaling, S. Guha, IBM

Oxide-based heterostructures, D. Schlom, Cornell U.

Some Observations Associated with Scaling Towards Technologically Relevant Critical Geometries, I. Thayne¹, S. Bentley¹, M. Holland¹, I. Povey², E. O’Connor², M. Pemble², P. K. Hurley², J. Ahn³, and P. McIntyre³, ¹U. Glasgow, UK, ²Tyndall National Institute, Ireland, ³Stanford U.

Cross-bar resistive memory using TiO₂ thin film, G. H. Kim¹, J. H. Lee¹, J. H. Han¹, S. J. Song¹, J. Y. Seok¹, J. H. Yoon¹, K. J. Yoon¹, M. H. Lee¹, T. J. Park², and C. S. Hwang¹, ¹Seoul National U., Korea, ²Hanyang U., Korea

MOS Interface Properties of Ge Gate Stacks based on Ge oxides and the Impact on MOS Device Performance, S. Takagi, R. Zhang, N. Taoka, and M. Takenaka, U. Tokyo, Japan

Pushing the material limits in high k dielectrics on high carrier mobility semiconductors. Is in-situ process the best choice?, M. L. Huang¹, W. C. Lee¹, T. D. Lin², Y. H. Chang¹, C. A. Lin¹, Y. C. Chang², T.-W. Pi³, J. Kwo^1,2, and M. Hong², ¹National Tsing Hua University, Taiwan, ²National Tsing Hua University, Taiwan, ³National Synchrotron Radiation Research Center, Taiwan

III-V 3D Transistors, P. D. Ye, J. J. Gu, and Y. Wu, Purdue U.

2010

Materials and Processes for High-k Metal Gate Stacks for 28 nm and Beyond, P. Kirsch, SEMATECH

High Performance InGaAs Quantum Well FETs with High-k Dielectrics, M. Radosavljevic, Intel

Nanowire Transistors: Performance Limits, Strain Engineering, Reduction of Parasitic Resistance, Y.-C. Yeo, National U. Singapore, Singapore

BiCS Flash Memory Technology, A. Nitayama, Toshiba, Japan

In-situ Studies of High-k Oxide Growth on III-V Semiconductors, C. L. Hinkle, UT Dallas

Understanding of GeO₂ Material Properties for Advanced Ge MIS Stacks, K. Kita, U. Tokyo, Japan

2009

Quality control of high-k gate oxides by doping with impurities: Guidelines from theoretical analysis, N. Umezawa, NIMS, Japan

Novel charge-based multiferroic composite heterostructures, C. A. F. Vaz, J. Hoffman, and C. H. Ahn, Yale U.

Gate Dielectrics, Interfaces, and SISC, T. P. Ma, Yale U.

Passivation of InGaAs and InAs by ALD Precursors, J. B. Clemens¹, E. A. Chagarov¹, M. Holland², R. Droopad³, J. Shen¹, and A. C. Kummel¹, ¹UCSD, ²U. Glasgow, UK, ³Texas State University - San Marcos

Fermi level pinning and its removal at III-V MOS interfaces, H. Hasegawa, M. Akazawa, Hokkaido U., Japan

Memory technology: Evolutionary versus revolutionary concepts, J. Van Houdt, imec, Belgium

How to improve mobility, performance, and BTI reliability of high-k/metal gate transistors?, X. Garros, M. Casse, G. Reimbold, F. Martin, F. Boulanger, LETI, France

2008

High-k/Metal Gate Technology: An Ode to Materials Research and Innovation, V. Narayanan, IBM

High k Dielectrics for Next Generations Non Volatile Memories, M. Alessandri¹, R. Piagge¹, A. Del Vitto¹, A. Sebastiani¹, C. Scozzari¹, C. Wiemer², L. Lamagna², G. Ghidini¹, and M. Fanciulli^2,3, ¹Numonyx, Italy, ²CNR INFM, Italy, ³Universits degli Studi Milano-Bicocca, Italy

Reliability Mechanisms in High-K & Metal-Gate Transistor Technology, S. Pae, J. Hicks, J. Jopling, J. Maiz, C. Prasad, M. Hattendorf, and J. Wiedemer, Intel

Physical Origin of V_TH Instability in High-k MOSFETs, A. Toriumi, U. Tokyo, Japan

Enabling Green Transistors with Narrow Bandgap Compound Semiconductors, S. Datta, Penn State U.

Interface Studies of Metal Oxide Gate Insulators on Ge and III-V Substrates, P.C. McIntyre¹, Y. Oshima^1,2, E. Kim¹, E. A. Chagarov³, J. Cagnon⁴, K. C. Saraswat¹, S. Stemmer⁴, and A. C. Kummel³, ¹Stanford U., ²TEL, Japan, ³UCSD, ⁴UCSB

Functional Oxide Heterostructures, A. Demkov, UT Austin

2007

Electron Transport in Bulk-Si NMOSFET's in Presence of High-k Gate Insulator, K. Maitra¹, M. Frank², V. Narayanan², B. P. Linder², E. Gusev³, V. Misra⁴, and E. Cartier², ¹AMD, ²IBM, ³Qualcomm, ⁴NCSU

Reversible and Irreversible Instabilities in High-k/Metal Gate Stacks, G. Bersuker, SEMATECH

Photoemission Study of Metal/High-k Dielectric Gate Stack, S. Miyazaki¹, H. Yoshinaga¹, A. Ohta¹, Y. Akasaka², K. Shiraishi³, K. Yamada⁴, S. Inumiya², M. Kadoshima², and Y. Nara², ¹Hiroshima U., Japan, ²Selete, Japan, ³U. Tsukuba, Japan, ⁴Waseda U., Japan

Resistance Switching Characteristics of Doped Metal Oxide for Non-Volatile Memory Applications, D. S. Lee, W. Xiang, R. Dong, D. J. Seong, and H. Hwang, GIST, Korea

Ge and III/V: the CMOS of the Future, M. Heyns^1,2, C. Adelmann¹, F. Bellenger¹, G. Brammertz¹, D. Brunco³, M. Caymax¹, B. De Jaeger¹, A. Delabie¹, G. Eneman¹, M. Houssa¹, B. Kaczer¹, D. Lin⁴, K. Martens¹, M. Meuris¹, J. Mittard¹, K. Opsomer¹, G. Pourtois¹, A. Satta¹, M. Scarrozza¹, E. Simoen¹, S. Sioncke¹, L. Souriau¹, V. Terzieva¹, and S. Van Elshocht¹, ¹imec, Belgium, ²U. Leuven, Belgium, ³Intel, ⁴Purdue U.

Structure and Composition of High-k Films on Alternative Channel Materials, L. Goncharova, O. Celik, C.-L. Hsueh, T. Feng, E. Garfunkel, and T. Gustafsson, Rutgers U.

First Principles Investigation of Defects at Semiconductor-Oxide Interfaces, A. Pasquarello, EPFL, Switzerland

2006

Challenges in achieving low PMOS Threshold Voltages with Metal Gate Electrodes on Scaled High-k Dielectrics, S. Samevadam, Freescale

Multi-Vibrational Hydrogen Release: A dielectric breakdown model for ultra-thin SiO₂/SiON and high-k stack, G. Ribes, STMicroelectronics, France

Embedded FRAM Technology, T. Moise, Texas Instruments

Opportunities for Advanced Technology in Telecommunications, L. Smarr, California Institute for Telecommunications and Information Technology

When defects approach a device size, A. Shluger, UCL, UK

What happens at high-k dielectric interfaces?, K. Shiraishi, U. Tsukuba, Japan

The search for a high performance metal gate/high-k n-mosfet, S. Guha, IBM

Opportunities and Challenges for high-k/III-V MOSFETs, P. Ye, Purdue U.

2005

Performance and threshold-voltage control in high-k/metal-gate FETs, E. Cartier, IBM

Device and Reliability Characteristics of HfSiON-CMOSFETs, M. Takayanagi, Toshiba

Interface Band Alignment at High-k/Metal Gate Structures: Interface Dipoles and Internal Fields, R. Nemanich, NCSU

Elementary Considerations in Reliability Physics: How a simple model illuminates the mechanism of NBTI Degradation, resolves a 40-year old puzzle, and establishes a protocol for lifetime extrapolation, M. A. Alam, Purdue U.

Floating Gate Flash Memory Technology, K. Parat, Intel

New Memory Concepts: from Silicon Nanocrystal Technologies to Molecular Memories, B. de Salvo, LETI, France

DRAM Memory Technologies, K. Kim and G. Jeong, Samsung

2004

Metal Gate Electrodes for CMOS Applications, V. Misra, NCSU

Atomic layer deposition of high-k gate dielectrics onto Ge and III-V semiconductors, M. M. Frank¹, V. K. Paruchuri¹, M. Copel¹, E. P. Gusev¹, H. Shang¹, D. Starodub², T. Gustafsson², E. Garfunkel², C.-L. Hsueh², Y. J. Chabal², J. Grazul³, D. A. Muller³, G. D. Wilk⁴, and M. Gribelyuk¹, ¹IBM, ²Rutgers U., ³Cornell U., ⁴ASM

Interface Passivation for SiO₂ on 4H-SiC, J. R. Williams¹, S. Wang¹, T. Isaacs-Smith¹, C. Ahyi¹, S. Dhar², A. Franceschetti², S. T. Pantelides², L. C. Feldman², and G. Chung³, ¹Auburn U., ²Vanderbilt U., ³Dow Corning

Silicon Nanocrystals: Physics and Memory Technologies, R. Muralidhar, R. Rao, R. F. Steimle, M. Sadd, C. T. Swift, B. Hradsky, S. Straub, T. Merchant, M. Stoker, S. G. H. Anderson, M. Rossow, J. Yater, B. Acred, K. Harber, E. J. Prinz, and B. E. White Jr, Freescale

Hydrogen interactions with semiconductors, oxides, and their interfaces, C. G. Van de Walle, UCSB

Ge Surface Passivation for High Performance MOSFETs, K. C. Saraswat, C. O. Chui, A. N., H. Kim, and P. McIntyre, Stanford U.

On the methodology for Reliability Characterization of MOS Devices with high-k Gate Dielectrics, A. Kerber, Infineon

2003

Challenges for Dual Metal Gate Electrodes on HfO₂ Gate Dielectrics, J. Schaeffer, Motorola

Integration of novel functional oxides with Si, A. Grishin, KTH, Sweden

First-principles calculations of the formation of the SrTiO₃/Si interfaces, P. E. Bloechl, Clausthal University of Technology, Germany

Creation mechanism of interface defects at the early stage of Si oxidation processes studied by UHV-ESR, S. Yamasaki, AIST, Japan

Recent Developments in Understanding Local Effects and Device Properties of Hf-based High-k Dielectrics, G. Wilk, ASM America

Development and Characterization of Stacked Gate Dielectrics on GaAs, M. Passlack, Motorola

Gate Dielectric Needs for Non-Classical CMOS, H.-S. P. Wong, IBM

Suppression of Subcutaneous Oxidation during the Deposition of Amorphous LaAlO₃ on Silicon, D. G. Schlom, Penn State U.

2002

Gate material issues for high-k gate dielectrics, T.-J. King, UC Berkeley

SiC MOSFETS and their interfaces, H. Yano, Nara Institute of Science and Technology, Japan

Electronic structure and band offsets in high-k dielectrics, J. Robertson, Cambridge U., UK

Electronic structure at Si/high-k dielectronic interfaces, G. Lucovsky, NCSU

Effects of interface states and charge trapping on the performance of high-k gate dielectrics devices, J. C. Lee, UT Austin

Charge trapping, mobility degradation and reliability of high-k gate stacks, E. Cartier ^1,2, A. Kerber^2,3, L. Pantisano³, R. Carter³, T. Kauerauf³, and R. Degraeve³, ¹IBM, ²SEMATECH, ³imec, Belgium

2001

Integration challenges for high-k gate stack engineering, H. R. Huff, A. Agarwal, L. Perrymore, C. Sparks, M. Freiler, G. Gebara, B. Bowers, P. J. Chen, P. Lysaght, J. Barnett, D. Riley, B. Nguyen, Y. Kim, J. E. Lim, S. Lim, G. Bersuker, P. Zeitzoff, G. A. Brown, C. Young, B. Foran, F. Shaapur, A. Hou, C. Lim, H. Alshareef, S. Borthakur, D. J. Derro, R. Bergmann, L. A. Larson, M. I. Gardner, J. Gutt, R. W. Murto, K. Torres, and M. D. Jackson, SEMATECH

Capacitively-detected magnetic resonance on semiconductor/oxide interfaces and field effect transistors, M. S. Brandt¹, T. Graf¹, R. T. Neuberger¹, M. Stutzmann¹, S. Baldovino² and M. Fanciulli², ¹TU Munchen, ²INFM, Italy

Impact of oxide breakdown on FET and circuit operation and reliability, B. Kaczer, R. Degraeve, A. De Keersgieter, K. Van de Mieroop, M. Rasras, V. Simons, P. J. Roussel, and G. Groeseneken, imec, Belgium

Characterization of post-soft breakdown conduction in ultra-thin oxides induced by ionizing radiation and constant voltage stress, J. S. Suehle, NIST

The 4H-SiC/SiO₂ interface, J. K. McDonald¹, A. Franceschetti¹, S. T. Pantelides¹, R. A. Weller¹, L.C. Feldman¹, G. Chung², C. C. Tin², J. R. Williams², C.-Y. Lu³, B. S. Um³, and J. A.Cooper Jr.³, and M. K. Das ⁴, ¹Vanderbilt U., ²Auburn U., ³Purdue U., ⁴Cree

Comparative study of high-k CVD films of Hf and Zr Silicate for CMOS devices, M. J. Bevan, M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, H. Bu, A. Shanware, D. E. Mercer, R. T. Laaksonen, and L. Colombo, Texas Instruments

High K gate dielectric university research, J. R. Hauser, NCSU

2000

N- and P-Channel FETs Built with HfOz and ZrO₂, S. A. Campbell, N. Hoilien, R. Smith, T. Z. Ma, and W. L. Gladfelter, U. Minnesota

High Power Devices in Silicon and Silicon Carbide, H. Lendenmann, F. Dahlquist, and P. Skytt, ABB Research

Theory of Oxide Breakdown, M. A. Alam, B. E. Weir, J. D. Bude, and P. J. Silverman, Lucent Technologies

Carrier Transport in Stressed Thin Gate Oxides, S. Takagi, Toshiba, Japan

Quasi-Breakdown vs. Hard Breakdown in Ultrathin SiO₂ Films: Beyond the Appearances, E. Vincent, S. Bruyere, D. Roy, and F. Monsieur, STMicroelectronics

Characterization of Ultrathin Films of Metal Oxides for CMOS Applications, D. A. Buchanan, IBM

Atomic Layer Deposition of Ultrathin Films using Sequential Surface Reactions, S. George, U. Colorado

1999

Tantalum Pentoxide (Ta₂O₅) as a Dielectric Film for Silicon-Based Devices, C. Chaneliere and J. L. Autran, INSA-Lyon, France

Surface Cleaning Issues in Thin-Oxide Technology, P. Mertens, imec, Belgium

Oxide Damage and Breakdown: the Crucial Role of Anode Injected Holes, J. C. Bude, B. E. Weir, P. J. Silverman, and M. A. Alam, Lucent Technologies

Defect Generation and Reliability of Ultra-Thin SiO₂ at Low Voltage, J. H. Stathis and D. J. DiMaria, IBM

Relationship Between Defect Site Generation and Dielectric Breakdown Studied by \""A-Mode\"" Stress Induced Leakage Current, K. Okada, Matsushita Electronics

Hydrogen Electrochemistry in Silica and Implications for MOSFETs, P. E. Bloechl, IBM, Switzerland

Interface Formation in the Growth of Oxides and Nitrides, Y. J. Chabal, K. T. Queeney, M. K. Weldon, and K. Raghavachari, Lucent Technologies

1998

Understanding the Evolution of Silicon Surface Morphology During Aqueous Etching, M. Hines, Cornell U.

Basic Mechanisms of Radiation Damage in Semiconductor Devices - Revisited with an Eye Towards the Future, P. Dressendorfer, Sandia

SOI Materials and Gate Oxide Reliability, D. Sadana, R. Bolam, F. Assaderaghi, G. Shahidi, and D. Badana, IBM

Electrical Characterization of Ultrathin Oxides, K. R. Farmer, New Jersey Institute of Technology

Characterization and Control of Ultrathin Oxide Interfaces, Y. Nishioka¹, K. Namba¹, M. Matsumura¹, T. Sakoda¹, Y. Kurnagai¹, T. Komeda¹, H. Kobayashi², T. Hoshino³, A. Ando⁴, and K. Miki⁴, ¹Texas Instruments, Japan, ²Osaka U., Japan, ³Chiba U., Japan, ⁴ETL, Japan

MOSFET Tunneling Issues in SiO₂ and Alternative Dielectrics - Challenges and Opportunities, H. Z. Massoud, J. P. Shiley, and A. Shanware, Duke U.

1997

Characterizing Individual Interface Traps with Charge Pumping, N. Saks, NRL

Present Status of Oxides on SiC, J. Palmour, Cree

Soft X-Ray Photoemission and Surface Infrared Studies of Model SiliconlSilicon Dioxide Interfaces: Does the Data Support A Fundamental Re-examination of How We Assign XPS Spectra of the Si/SiO₂ Interface?, M. Banaszak Holl, U. Michigan

Theoretical Study of Atomic Scale Processes at Si(001)-SiO₂ Interfaces, M. Hybertson, Lucent Technologies

Nanometer-Scale Studies of Oxide Charging and Hot-Electron Effects in MOS Structures Using Ballistic Electron Emission Microscopy, J. P. Pelz, OSU

EPR Studies of Interfaces and Volume Defects in Si/SiO₂ Structures with Ultrathin (<40 A) Oxide Layers, H. J. von Bardeleben and J. L. Cantin, CNRS, France

Flash Memory Technology and Reliability Issues Associated with SiO₂/Si Interfaces, K. Yoshikawa, Toshiba, Japan

1996

Electron Transport at the SiC/SiO₂ Interface, T. Ouisse, UMR-CNRS, France

Monte Carlo Simulation of MOS Devices, M.V. Fischetti and S. E. Laux, IBM

New Insights in the Impact of the Breakdown Mechanisms on the Statistics of Intrinsic and Extrinsic Breakdown in Thin Oxides, G. Groeseneken, R. Degraeve, J.-L. Ogier, R. Bellens, Ph. Roussel, M. Depas, and H.E. Maes, imec, Belgium

Application of Femtosecond Lasers to Nonlinear Spectroscopy and Process Monitoring of Si(001) Interfaces, M. C. Downer, J. I. Dadap, X. F. Xu, P. T. Wilson, M. H. Anderson, M. ter Beck, O. A. Akisipetrov, E. D. Mishina, N. M. Russell, and J. G. Ekerdt, UT Austin

STM Nanofabrication and Deuterium Post Metal Annealing of MOSFETs for Improved Hot Carrier Reliability, J. W. Lyding¹, K. Hess¹, and I. C. Kizilyalli², ¹UIUC, ²Lucent Technologies

Thin Gate Dielectrics for Future CMOS Applications, H. S. Momose, S-I. Nakamura, Y. Katsumata, and H. Iwai, Toshiba, Japan

1995

Structural and Electrical Characterization of Ultrathin Gate Oxides and Their Interfaces, M. Hirose, Hiroshima U., Japan

Medium Energy Ion Scattering of Silicon Oxidation in the 5 - 80 A Regime, E. Garfunkel, E. P. Gusev, H. C. Lu, and T. Gustafsson, Rutgers U.

Electrical Properties and Device Applications of Thermally Oxidized Silicon Carbide, J. A. Cooper Jr., Purdue U.

Transport Issues of STM-Injected Hot Electrons in Metal-Oxide-Semiconductor Structures, R. Ludeke, E. Cartier, and A. Bauer, IBM

Molecular Engineering using Thin Organic Films, M. C. Petty, U. Durham, UK

Science and Technology in the Development of Thin Film Transistor Liquid Crystal Displays, J. Batey, Xerox

Atomic Structure and Electrical Properties of Nitrided Si-SiO₂ Interfaces, G. Lucovski, D. R. Lee, Z. Jing, C. Parker, and J. R. Hauser, NCSU

1994

An Engineering Model of VLSI Gate Oxide Breakdown, C. Hu, UC Berkeley

Defect Production, Degradation, and Breakdown of Silicon Dioxide Films, D. J. DiMaria, IBM

MOSFET Based Sensors for Molecular Hydrogen at Ambient Temperatures Using Palladium Alloy Gates, R. C. Hughes, Sandia

Oxynitride Dielectrics Grown in N₂O and NO, Y. Okada and P. J. Tobin, Motorola

Measurement and Modeling of Several PMOSFET Hot-Carrier Degradation Mechanisms, R. Woltjer, Philips, The Netherlands

Cluster Analogs for Si/SiOz, Interfaces and Their Structural Implications, F. R. McFeely, IBM

In-situ TEM Study of Silicon Oxidation, J. M. Gibson, UIUC

1993

High-Quality Gate Oxide Films Based on Ultraclean Technology, T. Ohmi, Tohoku U., Japan

Silicon Surface and lnterface Roughness: The Use of Fractals, E. A. Irene, U. North Carolina

Ferroelectric Thin Films for Memory Applications, R. Moazzami, Motorola

Reactions of Atomic Hydrogen at the Si/SiO₂ Interface, E. Cartier, IBM

Physical Understanding of-Hot Carrier Stress in p-MOSFETs Relevant to Circuit Operation, W. Weber, M. Brox, A. v. Schwerin, and R. Thewes, Siemens, Germany

Structural Aspects of Intrinsic Defects at Thermally Grown Si/SiO₂ Interfaces Analyzed by ESR, A. Stesmans, U. Leuven, Belgium

Radiation and Hot-Electron Effects in SIMOX/MOSFETs, S. Cristoloveanu, LPCS, France

Self-Trapped Holes in Amorphous Silicon Dioxide Layers, D. Griscom, NRL

An Overview of Radiation Induced lnterface Traps and Other Defects, T. R. Oldham, F. B. McLean, H. E. Boesch, and J. M. McGarrity, ARL

SiO₂/Si(100) lnterface Roughness Measured with X-Ray Diffraction, M.-T. Tang, M. L. Green, D. Brasen, K. Krisch, L. Manchanda, G. S. Higashi, and T. Boone, AT&T

1992

Comparison of Electrical Techniques for Characterization of Si/SiO₂ Interface, D. K. Schroder, Arizona U.

Fundamental Considerations of Tunneling in MOS Structures, J. Maserjian, JPL

Spatially Resolved Characterization of SiO₂ with AFM/STM, M. P. Murrell, Cambridge U., UK

Understanding the Nature of Si/SiO₂ Interface Using XPS, P. J. Grunthaner, JPL

Theory of the Capture Cross-sections of the Pb centers, M. Lannoo, ISEN, France

Trap Creation Studies by EPR, J. Stathis, IBM

The Physics of Dielectrics for Charge Storage Capacitors and Non-volatile Memory, P. Balk, Delft U., The Netherlands

High-Dielectric Constant Films as SiO₂ Replacements in ULSI Devices, J. Scott, U. Colorado

Effects of Oxinitridation on Dielectric Properties of ScaIed MOSFETS and EEPROMs, H. Fukuda¹, M. Obara¹, and Y. Nishioka², ¹Texas Instruments, Japan, ²Tsukuba R&D Center, Japan

ULSI Technology and Interfaces: Future Directions, R. E. Howard, AT&T

Iron Disilicide on Silicon, H. Lueth, ISI, Germany

Wet Cleaning Strategy for Improved Gate Oxide Integrity, M. Heyns, imec, Belgium

Chemical Cleaning of Silicon Surfaces for ULSI, M. Hirose, Hiroshima U., Japan

Formation of Near Ideal Si/SiO₂ Interface, T. Hattori, Musashi Institute of Technology, Japan

1991

Recent Advances in the Theory of Silicon Dioxide, A. M. Stoneham, AEA Industrial Technology

Extremely High Electron Mobility in Si/Ge,Si Structures Grown by Molecular Beam Epitaxy, Y. H. Xie, E. A. Fitzgerald, D. Monroe, Y. J. Mii, F. A. Thiel, B. E. Weir, and L. C. Feldman, AT&T

Influence of Metal Contaminations on MOS Capacitors, M. Takiyama, S. Ohtsuka, and M. Tachimori, Nippon Steel, Japan

1990

Technology trends in dynamic RAMs: 64 Mb and beyond, H. Sunami, Hitachi, Japan

STM of the oxygenation of silicon at room temperature and 650 ºC, M. Welland, Cambridge U., UK

The theory of oxide defects near the Si-SiO₂ interface, W. Beall Fowler, Lehigh U.

Silicon and Si-Ge structures and devices by UHV chemical vapor deposition, B. Meyerson, IBM

Time dependent response of MOS systems to ionizing radiation, F. B. McLean, Harry Diamond Lab

Investigation of the different defect components in hot carrier stressing of nMOS transistors, B. Doyle and K. R. Mistry, DEC

1989

The Evolution and Scaling of DRAMS, R. H. Dennard, IBM

Hot-Electron Degradation in Devices, H. E. Maes, imec, Belgium

Defect and Electric Field Studies of the SiO,/Si Interface Utilizing Variable-Energy Positron Beams, K. G. Lynn, Brookhaven

Ultra-High Clean Oxides, T. Ohmi, Tohoku U., Japan

1988

Microstructural Aspects of the Si/SiO₂ lnterface, J. Bevk, AT&T

Low-Temperature Electron Spin Resonance Study of P_b Defects at Thermally-Grown Si/SiO₂ Interfaces, A. Stesmans, U. Leuven, Belgium

Interface States Generated by Electrons and Holes, S. Lyon, Princeton U.

Engineering Model of Defect-Induced Oxide Breakdown, C. Hu, UC Berkeley

Characterization of Individual Traps in SiO₂/Si, M. J. Schulz, U. Erlangen-Numberg, Germany

1987

Characterization of SiOx on Si by STM: Identification of Individual Trapping Sites, R. Koch, IBM

Interface Damage in MOS Structures due to Radiation and Hot Carriers, J. T. Nelson, AT&T

Electronic Structure of P_b Center at SiO₂/Si Interface, M. Cook, NRL

Hot Carrier Transport and Degradation Effects in Small MOSFFTs, J. F. Koch, TU Munich, Germany

Studies of Interface Traps by Tunneling in Very Thin Oxides, R. A. Buhrman, Cornell U.

1986

Hot carrier trapping in short channel MOSFETs, C. Werner and W. Weber, Siemens, Germany

InP-MISFETs: An alternative to Si-nMOS, K. P. Pande, Allied Corporation

Buried oxide silicon-on-insulator technology development, D. Chen, Texas Instruments

Electrical properties of Si/CoSi/Si metal base transistors, E. Roscecher, CNET

1985

1984

Defect Structures in Amorphous SiO₂ and at SiO₂/Si Interface, D. L. Griscom, NRL

Chemical Characterization of Interfaces in Silion Device Structures, C. R. Helms, Stanford U.

The Quantum Hall Effect, D. C. Tsui, Princeton U.

Modulation-Doped Heterojunction FETs, T. J. Drummond, Sandia

Process Implications of Semiconductor Interfaces for VLSI, R. C. Joy, Gould AMI Semiconductors

Generation of Interface States - A Critical Review of Data and Models, P. Balk, Aachen Technical U., Germany

1983

MOS Measurements: A Historical Perspective and the Current State of the Art, E. H. Nicollian, U. North Carolina

High Resolution Electron Microscopy of Interfaces in Semiconductors, R. Sinclair, Stanford U.

SIMS Characterization of Silicon Device Materials, C. W. Magee, RCA

Substrate and Surface Effects on GaAs Integrated Circuits, C. P. Lee, Rockwell International

Role of Interfacial Oxides in Bipolar Devices, B. H. Yun, IBM

Charge Tunneling, Trapping, and Device Degradation in Thin SiO₂, C. M. Hu, UC Berkeley

Electron Heating in SiO₂, D. J. Maria, IBM

1982

1981

1980

1979

The Outer Limits of Si VLSI, J. L. Moll, HP Labs

Beam Annealing at Interfaces and Near-Interface Regions, J. F. Gibbons, Stanford U.

1978

1977

1976

1975

1974

1973

1968

1967

1965